1. Field of the Invention
This invention relates to the field of floating point math processors in computer systems. More particularly, this invention relates to floating point remainder generators in math processors.
2. Art Background
A common method of improving speed of a computer system is to employ a math processor for performing mathematical calculations. The combination of a processor and the math processor provides greatly increased speed of system operation, since math processors are optimized for performing mathematical calculations, and since the burden of performing specialized calculations is lifted from the processor. Tasks typically delegated to a math processor include floating point addition, subtraction, multiplication and division.
A useful function for hardware implementation in a math processor is the floating point remainder (REM) function. The REM function requires a math processor to divide a floating point number "X" by another floating point number "Y" to generate an integer quotient, and deliver the remainder corresponding to the quotient. The REM function improves system accuracy, and is particularly useful in argument reduction for periodic functions like sin and cos, as well as table driven methods for computing functions such as arctan. The REM function provides higher precision for many other functions since the remainder delivered is always exact. In addition, the REM function is useful in cryptography and password recognition.
Previous math processors used single digit (1 bit of quotient per clock radix 2) restoring or non-restoring division steps to generate the REM function. However, this method is time-consuming since the number of division steps required roughly equals the difference between the floating point exponent values of X and Y.
As will be disclosed, the present invention provides a method and apparatus for improving the speed of the REM function by implementing a radix 4 SRT non-restoring method of division (which yields twice as many digits per divide step as radix 2 non restoring division), terminating with at most one single bit restoring division step.